Many VLSI chips currently manufactured have one or more random access memories (RAM) embedded within the chip as part of an overall device. The RAM, because it is an integral part of the chip, needs to be tested to determine whether it will function properly. Testing of the RAM may be achieved in one of two ways. The first method involves the use of an external testing device for accessing and manipulating the RAM. Because the RAM is embedded within the chip, it is very difficult for the external testing device to access the RAM. Hence, testing using the external testing method is difficult and inefficient. An alternative testing method involves the use of a built-in self-test (BIST) mechanism which is incorporated into the chip to enable the chip to test its own RAM. Because the BIST mechanism is a part of the chip and, hence, is internal to the chip, it does not experience any difficulties in accessing the RAM. Thus, the BIST mechanism tests the RAM much more effectively and efficiently than the external device. For this reason, many VLSI chips include a BIS T mechanism for testing on-chip RAM.
A typical BIST mechanism includes a test pattern generator and a test response evaluator. The test pattern generator generates pseudo-random patterns for the data and addresses and feeds these to the RAM. The test response evaluator, in turn, implements a compaction method (such as signature analysis) to evaluate the output data from the RAM. From the evaluation of the RAM output data, the BIST mechanism determines whether the RAM exhibits any faults.
A shortcoming of the current BIST mechanisms is that they cannot guarantee complete fault coverage for certain RAM fault models. This is due to the fact that, in traditional BIST techniques, fault coverage is estimated through fault simulation. Instead of simulating all possible faults (which is computationally impractical), only a sample of faults is simulated. This means that the fault determination of the BIST mechanism represents only a probability that the RAM is fault free. As with all probabilities, there is a chance that the RAM may have faults despite the fact that it passed the BIST test. For systems which demand high reliability, this possibility of error cannot be tolerated. High reliability systems require a BIST method and apparatus which can guarantee that any instance of certain fault models will be detected. Currently, there is no BIST mechanism believed to be available which can guarantee fault coverage for certain RAM fault models.